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The thin copper laminate process does not need special technology such as sputtering, therefore it is relatively easy to design the manufacturing process. Figure 63.17 illustrates a typical manufacturing process for the double-side circuits. 1. It starts from double-side laminates with very thin copper layers. 2. The first step is drilling to form the via holes. Most of the drilling technologies are available to generate the small holes. Mechanical process including micro punching works for larger holes than 60 microns diameters. Chemical etching and plasma etching could be the low cost solutions for the high hole counts designs. But they need supplemental photolithography and copper etching process. Excimer laser and UV YAG laser are capable to generate smaller holes than 50 micron diameters for both through holes and blind via holes. 3. Copper layers are plated on the whole surface to build the conductive layer in the via holes, by both electroless and electrolytic processes, using, standard copper plating process. It is important that the processes are controlled well enough to make the thin copper layers with uniform thickness. 4. A negative pattern of conductor traces for the plating resist is formed on the copper surface by a high-resolution photolithography process. 5. Further electro plating is conducted to build the required copper thickness. The plating conditions should be well controlled to have a uniform thickness for whole circuits. A smaller panel size is recommended for an easy control of the plating conditions. 6. The plating resist is removed by standard stripping process. 7. As the final process, the seed layers between the conductor traces are removed by appropriate etching process. A supplemental metal plating is conducted as the protection layer for the process, prior to the stripping process of the plating resist.

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Figure 63.18 and Fig. 63.19 show examples made by the semi-additive process. The sputtering process has been developed to have thin seed layer for the semi-additive process with finer trace densities as shown in Fig. 63.20.

16:

FIGURE 63.19 Fifteen micron traces with 20 micron holes for 10 layer circuits. (Source: MicroComnex.)

note These are the pin connections to the Propeller,

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1. Because it s a plain plastic film, polyimide film is typically the starting material for the manufacturing process. 2. The small size holes are generated by mechanical processes or laser process. It needs supplemental photolithography process to use chemical etching and plasma etching for this process. 3. A set of sputtering processes is employed to form the electrically conductive thin seed layer, typically thinner than one micron. To have a reliable bond strength between organic layers and conductors, appropriate conditioning including surface treatment should be conducted. The following processes are used for plating resist formation:

Electro-forming of the copper conductors Stripping of the plating resist Etching of the seed layers A process that is basically the same as the previous semi-additive process, but is able to provide finer pitches with higher aspect ratios because of extremely thin seed layers. An optimized condition of the process can produce smaller than 5 micron pitches and larger aspect ratios than 1:5.

FIGURE 63.21 Ultra thin patterns made by semi-additive process with sputtering, (a) Ten micron pitch traces with one micron thick trace, (b) Ten micron wide traces with 25 micron thick traces. (Dynamic Research.)

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A combination of the semi-additive process with a casting technology of the polyimide resin provides a capability to build multi-layer constructions with ultra fine traces and micro via holes. But the layer constructions and the manufacturing process could be very different from the traditional flex circuits. The manufacturing process starts from the preparation of the base layer. A commercialized polyimide film is available as the starting material for the process.

A casting of the liquid polyimide on a suitable carrier plate is another choice to have a thinner base layer than 12 microns A glass or a stainless steel plate is recommended to use to manage the dimensions stable 1 A seed layer is formed on the base layer by a series of sputtering processes 2 A negative pattern of conductor traces is formed with plating resist by a high resolution photolithography process The selection of the photo resist could be the key of the technologyA spin coating of the liquid photo resist is recommended for the high resolution 3 An electrical forming of copper or other suitable metals is conducted to generate the fine conductor traces with necessary aspect ratios 4 A set of process for stripping and etching of the seed layer between conductor traces is conducted to have isolated circuits.

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A gold plating on the conductors prior to the stripping process is recommended for the chemical protection of the traces 5 A polyimide resin is coated on the circuits as the insulation layer for the next conductor layer A photo-sensitive polyimide resin is recommended to coat to generate via holes by photolithography process A combination of non-photo sensitive polyimide and Excimer laser is another choice It has a flexible capability to form reliable insulation layers But its productivity is low and processing cost per unit area is relatively high 6 The second seed layer is formed by the same sputtering process as shown previously in process 2 A difference is that the thin seed layer have to cover the different surfaces in the via holes 7.